This invention relates to a semiconductor circuit on a large scale integrated circuit(LSI). In particular, it relates to a complementary source follower circuit of a MOS (metal oxide semiconductor) LSI that is suitable for an output buffer of an analog circuit.
FIG. 1 shows a conventional CMOS (complementary MOS) drain follower circuit. In FIG. 1, there are two transistors, a P-channel MOSFET (metal oxide semiconductor field effect transistor) and an N-channel MOSFET. Each transistor has a source (S), a drain (D), a gate (G), and a body (B). This circuit can be used to invert signals, i.e., to convert a logical xe2x80x9c0xe2x80x9d into a logical xe2x80x9c1xe2x80x9d and a logical xe2x80x9c1xe2x80x9d into a logical xe2x80x9c0,xe2x80x9d where a logical xe2x80x9c0xe2x80x9d is represented by the voltage Vss and a logical xe2x80x9c1xe2x80x9d is represented by the voltage Vcc. The logical xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d signal is supplied to xe2x80x9cINxe2x80x9d and the inverted logical xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d signal is sent to xe2x80x9cOUT.xe2x80x9d The voltages Vss and Vcc are kept constant during the operation of the circuit. Each of the transistors should be xe2x80x9coffxe2x80x9d when the other transistor is xe2x80x9conxe2x80x9d but there is some overlap when both transistors will be xe2x80x9con,xe2x80x9d resulting in a xe2x80x9cDC pathxe2x80x9d with a current flow, Id, from Vcc to Vss. This current flow is wasted power.
FIG. 2 illustrates the relationship between the voltage at IN in FIG. 1(Vin along the horizontal axis) and the voltage at OUT in FIG. 1 (Vout along the right vertical axis) and shows that as Vin approaches the voltage Vcc, Vout approaches the voltage Vss and as Vin approaches the voltage Vss, Vout approaches the voltage Vcc. The left vertical axis gives the current Id (dotted curve) that flows as Vin increases along the horizontal axis from Vss to Vcc and shows that when Vin is about midway between Vss and Vcc there is a current flow Id, which is lost power.
The circuit of FIG. 1 is useful for processing digital signals because digital signals consist of a logical 0 or a logical 1, and intermediate levels where power is lost occur only during transitions between them. However, as circuits shrink, it is becoming possible to perform both digital and analog functions on a single chip, which is especially desirable for wireless and mobile applications.
FIG. 3 shows an example of an analog signal. This signal consists of many intermediate voltage levels. When an analog signal is inputted to conventional CMOS circuit, such as that of FIG. 1, the current Id flows almost constantly because the voltage is at intermediate levels so much of the time.
FIG. 4 shows a complementary source follower circuit similar to the complementary drain follower circuit of FIG. 1, where the sources, rather than the drains, are connected to the xe2x80x9cOUTxe2x80x9d voltage. FIG. 5 is similar to FIG. 2 but shows (horizontal axis and right vertical axis) that as the INPUT voltage in FIG. 4 increases from Vss to Vcc the OUTPUT voltage Vout increases from Vss to Vcc. FIG. 5 also shows (horizontal axis and left vertical axis) that there is a small current loss Id (dotted curve)at a voltage intermediate between Vss and Vcc. The level of current Id depends on the threshold voltage conditions. When the voltage applied to the transistors does not exceed their threshold voltages, both transistors are in an off condition and there is no xe2x80x9cIdxe2x80x9d current flow. For that reason, source follower circuits are attractive for merged digital-analog systems.
FIG. 6 shows a source follower circuit having an active load. But in the circuit of FIG. 6, when the transistor is xe2x80x9conxe2x80x9d a current steadily flows between Vcc and Vss, which increases power consumption. Also, the driving power is low because the current is shared between both the active load and the output load.
In order to reduce the power consumption and the driving power loss, a complementary source follower circuit can be used as shown in FIG. 7. This circuit can be realized using a bulk semiconductor substrate such as a single crystal silicon N-type or P-type substrate, but for a P-type substrate the source-to-body connection of the N-channel transistor is eliminated (as in FIG. 7) and for an N-type substrate the source-to-body connection of the P-channel transistor is eliminated (not shown).
However, eliminating the source-to-body connection in FIG. 7 results in non-linearity between the output voltages of the two transistors because the characteristics of the two transistors are not symmetrical.
In U.S. Pat. No. 5,463,240, a complementary source follower circuit on a common substrate is achieved by isolating each P-channel and N-channel transistor from the common semiconductor substrate. In laid open Japanese Patent No. 2000-323720 by the instant inventor, an SOI (silicon on insulator) substrate is used and in that invention no additional mask or circuit is needed, because on an SOI substrate each transistor can be isolated from other transistors and from the substrate.
As shown in FIG. 8, the linear relationship between input voltage Vin and output voltage Vout shown in FIG. 5 is offset when both transistors are xe2x80x9coffxe2x80x9d at the same INPUT voltage. Non-linearity occurs because the INPUT voltage is lower than the threshold voltages of the transistors. This creates a xe2x80x9cdead gapxe2x80x9d at an intermediate voltage between Vss and Vcc where both transistors are xe2x80x9coffxe2x80x9d and the voltage at the OUTPUT node is open. This dead gap can be tolerated when the signal is digital, but it distorts an analog signal. Improvements in the linearity between the input signal and the output signal are needed in order to permit a source follower circuit to process analog signals.
The circuit shown in FIG. 9 is similar to the circuit shown in FIG. 4 except that a voltage VthN is added to the input voltage Vin going to the N-channel MOSFET and a voltage VthP is subtracted from the input voltage Vin going to the P-channel MOSFET. As shown in FIG. 10, these shifts in the two input voltages shift the voltage output Vout to the dotted line, thereby eliminating the dead gap.
In U.S. Pat. No. 6,333,623, a source follower circuit is used as a voltage regulator because a source follower circuit has low output impedance. In this patent, level shift circuits are also disclosed. In this patent, a level shift circuit is applied to the input node (IN) of the complementary source follower circuit to solve the dead gap problem. Also, a source follower circuit is used as a voltage regulator because a source follower circuit has low output impedance. In this patent, level shift circuits are also disclosed.
In the above patents, in order to realize complementary source follower circuits additional manufacturing processes are needed and, in order to solve dead gap problem, additional circuits, such as a level shift circuit, are needed.
An object of the present invention is to provide a high performance, area-efficient complementary source follower circuit that can be fabricated by conventional CMOS technology, without the need for special manufacturing processes or structural modifications.
Another object of the present invention is to avoid the use of additional circuits and the placing of limitations on the use of the circuit and instead to employ standard devices available in high performance CMOS logic technology.
Pursuant to these and other objectives, one embodiment of the present invention comprises a complementary source follower circuit having P-channel and N-channel MOSFETs, where the threshold voltage of each MOSFET is independently controlled by a back bias control circuit from which control signals are sent to each of the source and body terminals. In the circuit of this invention, a drain of one MOSFET is connected to the ground level and the drain of the other MOSFET is connected to the supply voltage, both gate terminals are connected to each other as an input node, and both source terminals are connected to each other as an output terminal node. There are no signal line connections from either source or either drain to the body and there is no signal line connection from the back bias circuit to the drain.
A significant and novel feature of the present invention is that there is usually no need for an additional circuit such as a level shift circuit (though one can be used, if desired or needed), which results in less time delay. In addition, because each transistor""s threshold voltage can be controlled over a wide range, the.power consumption can be reduced when the circuit is in stand-by mode.
Another advantage of the present invention is that it can be used to eliminate of the dead gap.
In another embodiment of this invention, an SOI substrate is used.
In this invention, analog and digital signal circuits can be combined on one chip without any additional manufacturing processes such as masking.